datasheet low emi clock generator mk1707 idt? low emi clock generator 1 mk1707 rev k 031611 description the mk1707 generates a low emi output clock from a clock input. the part is designed to dither the lcd interface clock for flat panel graphics controllers. the device uses idt?s proprietary mix of analog and digital phase locked loop (pll) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several db. the mk1707 offers both centered and down spread from a high speed clock input. refer to the mk1714-01/02 for a crystal input and the widest selection of input frequencies and multipliers. idt offers many other clocks for computers and computer peripherals. consult us when you need to remove crystals and oscillators from your board. features ? packaged in 8-pin soic ? pb-free package ? industrial temperature range available ? provides a spread spectrum output clock ? supports ati?s flat panel controllers ? guaranteed to +85 c operation ? accepts a clock input, provides same frequency dithered output ? good for all vga modes from 80 to 167 mhz ? peak reduction by 7db - 14db typical on 3rd - 19th odd harmonics ? low emi feature can be disabled ? includes power-down ? operating voltage of 3.3 v or 5 v ? advanced, low-power cmos process block diagram pll clock synthesis and spread spectrum circuitry iclk input buffer s1:0 spread direction low emi enable clock out 2 gnd vdd
mk1707 low emi clock generator sscg idt? low emi clock generator 2 mk1707 rev k 031611 pin assignment spread di rection and percentage select table 0 = connect to gnd m = unconnected (floating) 1 = connect directly to vdd pin descriptions iclk vdd gnd s1 clk s0 lee sd 1 2 3 4 8 7 6 5 8 pin (150 mil) soic sd pin 8 s1 pin 7 s0 pin 6 spread direction spread percentage (%) 00 0down 0.6 00 mdown 0.8 00 1down 1.25 0m 0 down center +0.5, -1.5 0m mdown 2 0m 1 down center +0.5, -2.5 01 0 down center +0.5, -3 01 mdown 5 01 1 power down - 10 0 center 0.35 10 mcenter 0.5 10 1center 0.7 1m 0center 0.8 1m mcenter 1.1 1m 1center 1.4 11 0test test 11 mcenter 2.5 11 1 power down - pin number pin name pin type pin description 1 iclk input connect to graphics input clock. 2 vdd power connect to +3.3 v. 3 gnd power connect to ground. 4 clk output spread spectrum clock output per table above. 5 lee input low emi enable. turns on spread spectrum when high. internal pull-up resistor. 6 s0 input function select 0 input. selects spread amount and direction per table above. internal mid-level. 7 s1 input function select 1input. selects spread amount and direction per table above. internal mid-level. 8 sd input spread direction select input. selects the direction of spread per table above. internal pull-up resistor.
mk1707 low emi clock generator sscg idt? low emi clock generator 3 mk1707 rev k 031611 external components the mk1707 requires a minimum number of external components for proper operation. decoupling capacitor a decoupling capacitor of 0.01f must be connected between vdd and gnd on pins 2 and 3, as close to these pins as possible. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb trace between the clock output and the load is over 1 inch, series termination should be used. to series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 . tri-level select pin operation the s1, s0 select pins are tri- level, meaning they have three separate states to make the selections shown in the table on page 2. to select the m (mid) level, the connection to these pins must be eliminated by either floating them originally, or tri-stating the gpio pins which drive the select pins. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guide lines should be observed. 1) the 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between the decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. 2) to minimize emi, the 33 series termination resistor (if needed) should be placed close to the clock output. 3) an optimum layout is one with all components on the same side of the board, minimi zing vias through other signal layers. other signal traces should be routed away from the mk1707. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. powerup considerations to insure proper operation of the spread spectrum generation circuit, some precautions must be taken while utilizing the mk1707. 1. an input signal should not be applied to iclk until vdd is stable (within 10% of its fina l value). this requirement can easily be met by operating the mk1707 and then iclk source from the same power supply. 2. lee should not be enabled (taken high) until after the power supplies and input clock are stable. this requirement can be met by direct control of lee by system logic - for example, a ?power good? signal. another solution is to leave lee unconnected to anything but a 0.01 f capacitor to ground. the internal pullup resistor on lee will charge the capacitor and provide approximately a 700 s delay until spread spectrum is enabled. 3. if the input frequency is changed during operation, disable spread spectrum until the input clock stabilizes at the new frequency.
mk1707 low emi clock generator sscg idt? low emi clock generator 4 mk1707 rev k 031611 absolute maximum ratings stresses above the ratings listed below can cause perm anent damage to the mk1707. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operat ional sections of the specif ications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics unless stated otherwise, vdd = 3.3 v , ambient temperature 0 to +85 c item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature, commercial 0 to +85 c ambient operating temperature, industrial -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +85 c power supply voltage (measured in respect to gnd) +3.135 +5.5 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.135 5.5 v supply current idd no load, at 3.3 v 20 ma idd no load, at 5 v 31 ma iddpd s0=s1=sd=1 60 a input high voltage v ih iclk (vdd/2) + 1 vdd/2 v input low voltage v il iclk vdd/2 (vdd/2) - 1 v input high voltage v ih s1, s0 vdd-0.5 v input high voltage v ih other inputs 2.5 v input low voltage v il s0, s1, sd, lee pins 0.5 v output high voltage v oh cmos, i oh = -4 ma vdd-0.4 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = -12 ma 0.4 v input capacitance c in s0, s1, sd, lee pins 5 pf
mk1707 low emi clock generator sscg idt? low emi clock generator 5 mk1707 rev k 031611 ac electrical characteristics unless stated otherwise, vdd = 3.3 v , ambient temperature 0 to +85 c thermal characteristics parameter symbol conditions min. typ. max. units input/output clock frequency 80 167 mhz input clock duty cycle time above vdd/2 20 80 % output clock duty cycle time above 1.5 v 40 50 60 % output rise time t or 0.8 to 2.0 v 1.5 ns output fall time t of 2.0 to 0.8 v 1.5 ns modulation frequency 19 41 khz emi peak frequency reduction 3rd - 19th odd harmonics 7 to 14 db parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 150 c/w ja 1 m/s air flow 140 c/w ja 3 m/s air flow 120 c/w thermal resistance junction to case jc 40 c/w
mk1707 low emi clock generator sscg idt? low emi clock generator 6 mk1707 rev k 031611 package outline and package dimensions (8-pin soic, 150 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information note: ?lf? denotes pb (lead) free package. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature mk1707slf mk1707sl tubes 8-pin soic 0 to +85 c mk1707slftr mk1707sl tape and reel 8-pin soic 0 to +85 c MK1707SILF mk1707sil tubes 8-pin soic -40 to +85 c MK1707SILFtr mk1707sil tape and reel 8-pin soic -40 to +85 c index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
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